ENEL 353 Fall 2019 Section 02 Lecture Page

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Last modified: Fri Dec 6 15:11:19 MST 2019

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Here you will find links to PDFs of lecture slides, PDFs of lecture notes, and related material, for section 02, Steve Norman's lecture section.

Slides, in PDF format

Lecture-by-lecture information

Below is lecture information in reverse chronological order. References to slides are exact for lectures that have already happened, and estimated for future lectures.

Day Date Lecture topics, references to slide sets and textbook Doc
Fri Dec 6 More final exam review.
Slides: Exam Review Slides
Wed Dec 4 Completion of Exercise 5 from the Tue Dec 3 tutorial. Completion of the material on shift registers (which are not an exam topic). Very brief remarks about PLAs (which are also not an exam topic). A problem from an old exam.
Slides: Set 10, slides 9-14 and 59-73; Exam Review Slides, slides 1-6
Textbook reference: Sections 5.4.2, 5.6.1
Mon Dec 2 Implementation of ROM arrays with NMOS transistors. Writes and reads to SRAM arrays. Floating-gate transistors and EEPROM arrays. Introductory remarks about shift registers.
Slides: Set 10, slides 33-55, 8-11
Textbook reference: Sections 5.5.1, 5.5.6, 5.5.3, 5.4.2
Fri Nov 29 Remarks about final exam topics. Quick remarks about counter circuits. Introduction to memory arrays. ROM and RAM. Bit cells, wordlines, and bitlines. Dot notation for ROM circuits. ROM-based implementation of logic functions.
Slides: Set 10, slides 1-6, 15-32
Textbook reference: Section 5.5.1
Wed Nov 27 Use of synchronizers to avoid metastability in circuits that have edges in their inputs at unpredictable times. Some insight into circuits, setup times, and metastability.
Slides: Set 9, slides 42-62
Textbook reference: Sections 3.5.4, 3.5.5
Mon Nov 25 Completion of an example setup- and hold-time problem. Clock skew. Derivation of setup- and hold-time constraints for synchronous sequential circuits with clock skew. Possible effects of setup- and hold-time violations, including metastability.
Slides: Set 9, slides 26-45
Textbook reference: Sections 3.5.2-3.5.4
Fri Nov 22 Derivation of setup- and hold-time constraints for synchronous sequential circuits. Example applications of setup- and hold-time constraints.
Slides: Set 9, slides 16-26
Textbook reference: Section 3.5.2
Wed Nov 20 Completion of example of deriving an FSM from a schematic. Introduction to timing considerations for synchrounous sequential circuits. The setup- and hold-time aperature. Four essential timing parameters for DFFs and DFF-based registers.
Slides: Set 8, slides 55-58; Set 9, slides 1-17
Textbook reference: Sections 3.4.5, 3.5 (introduction), 3.5.1, 3.5.2
Mon Nov 18 Final remarks about the sequence detector examples. Factored FSM design. Deriving an FSM from a schematic.
Slides: Set 8, slides 47-58
Textbook reference: Sections 3.4.3-3.4.6
Mon-Fri Nov 11-15 No lectures. Fall Break week. n/a
Fri Nov 8 An example sequence detection problem. Specifications for Moore and Mealy FSMs for that example. State transition diagram for the Moore FSM. Complete solution for the Mealy FSM.
Slides: Set 8, slides 43-47
Textbook reference: Section 3.4.3
Wed Nov 6 Concluding remarks about the traffic light controller FSM. Overview of steps in FSM design. Two different implementations of a clock-divide-by-3 FSM. Introduction to sequence detection problems.
Slides: Set 8, slides 24-43
Textbook reference: Sections 3.4.1–3.4.3
Mon Nov 4 The traffic light controller FSM: specification, state transition diagram, state encoding, truth tables for next-state logic and update logic, implementation using logic gates and a 2-bit state register.
Slides: Set 8, slides 15-24
Textbook reference: Section 3.4.1
Fri Nov 1 N-bit registers made from DFFs. Enabled, resettable and settable DFFs. Difference between synchronous and asynchronous reset and set inputs. Synchronous sequential circuit composition rules. Introduction to finite state machines (FSMs). Organization of Moore FSMs and Mealy FSMs.
Slides: Set 7, slides 35-45; Set 8, slides 1-15
Textbook reference: Sections 3.2.4-3.2.6, 3.3, 3.4 up to the start of 3.4.1
Wed Oct 30 Basic behaviour of a D flip-flop (DFF). Implementation of a DFF with two D latches. A clock divider circuit made with an inverter and a DFF.
Slides: Set 7, slides 1-35
Textbook reference: Sections 3.2.2, 3.2.3
Mon Oct 28 Introduction to sequential logic. SR latches. Clock signals. D latches.
Slides: Set 6, slides 1-18
Textbook reference: Sections 3.1, 3.2 up to the end of 3.2.2
Fri Oct 25 Propagation delay and contamination delay for combinational circuits built from combinational elements. Example propagation delay and contamination delay calculations. Glitches.
Slides: Set 6, slides 34-44
Textbook reference: Section 2.9
Wed Oct 23 More about decoders. Introduction to timing of combinational logic. Propagation delay and contamination delay for combinational devices.
Slides: Set 6, slides 20-34
Textbook reference: Sections 2.8, 2.9
Mon Oct 21 N-to-1 muxes with N greater than 4. Using muxes to implement logic functions. N-to-1 muxes where N is not a power of two. Introduction to decoders. Using decoders to implement logic functions.
Slides: Set 6, slides 10-19
Textbook reference: Section 2.8.
Fri Oct 18 No lecture. The instructor was out of town. n/a
Wed Oct 16 5-variable K-maps. Quick overview of minimization for problems with multiple outputs—this is not quiz, midterm or exam material in 2019. Introduction to multiplexers (muxes). 2-to-1 mux functionality and implementations. 4-to-1 mux functionality and implementations.
Slides: Set 5, slides 73-84; Set 6, slides 1-10
Textbook reference: Sections 2.7, 2.8.
Mon Oct 14 No lecture. Thanksgiving holiday. n/a
Fri Oct 11 Another K-map example for a function with don't-care outputs. Don't-care inputs in truth tables. Minimal POS expressions. K-map methods for finding minimal POS expressions.
Slides: Set 5, slides 55-72
Textbook reference: Section 2.7
Wed Oct 9 K-map problems in which essential prime implicants don't cover all the 1-cells. Don't-care outputs in truth tables. Introduction to K-map methods for functions that have don't-care outputs.
Slides: Set 5, slides 42-55
Textbook reference: Section 2.7
Mon Oct 7 Finding products associated with groups of 1-cells in K-maps. Imprecise description of K-map minimization methods. Implicants, prime implicants, distinguished 1-cells and essential prime implicants.
Slides: Set 5, slides 26-42
Textbook reference: Section 2.7
Fri Oct 4 Introduction to Karnaugh maps (K-maps). Adjacency in Boolean algebra and K-maps. Layout of 4-variable K-maps. Groupings of 1-cells.
Slides: Set 5, slides 1-26
Textbook reference: Section 2.7
Wed Oct 2 More about bubble-pushing. X and Z values at nodes in logic circuits. A simple model for operation of CMOS logic gates. Tristate buffers.
Slides: Set 4, slides 22-34
Textbook reference: Sections 2.5, 2.6
Mon Sep 30 More about using Boolean algebra to simplify expressions. Guidelines for drawing digital circuit schematics. The definition of minimal SOP expression. Two-level and multilevel combinational logic. Bubble-pushing with NAND and NOR gates.
Slides: Set 3, slides 48-50; Set 4, slides 1-21
Textbook reference: Sections 2.3, 2.4, 2.5
Fri Sep 27 Axioms and theorems of Boolean algebra. DeMorgan's Theorem and its relationship to NAND and NOR gates. Use of theorems to simply Boolean expressions.
Slides: Set 3, slides 33-48
Textbook reference: Section 2.3
Wed Sep 25 Minterm numbering aand shorthand for SOP canonical form. POS expresssions and POS canonical form. Use of POS canonical form to get a Boolean equation from a truth table. Maxterm numbering. Axioms of Boolean algebra; introduction to theorems of Boolean algebra.
Slides: Set 3, slides 22-35
Textbook reference: Sections 2.2, 2.3
Mon Sep 23 Introduction to Boolean algebra. Variables, literals, products, minterms, sums, maxterms. Example of proof by perfect induction. SOP expressions. Using SOP canonical form to get a Boolean equation from a truth table.
Slides: Set 3, slides 1-22
Textbook reference: Section 2.2
Fri Sep 21 Electrical connections for logic gates. Voltage levels for reliable operation of interconnected gates. Inputs, outputs, elements and nodes. Rules for combinational composition.
Slides: Set 2, slides 26-45
Textbook reference: Sections 1.6 and 2.1
Wed Sep 18 Gray codes and shaft encoders. Definitions of combinational logic and sequential logic. Basic logic gates: NOR, buffer, AND, OR, XOR, NAND, NOR, XNOR. Gates with 3 or more inputs.
Slides: Set 1, slides 77-82; Set 2, slides 1-27
Textbook reference: Section 1.5
Mon Sep 16 Overflow in addition of two's-complement numbers, review of overflow in unsigned addition; rules for detecting overflow. BCD encoding of integers. Gray codes.
Slides: Set 1, slides 57-78
Textbook reference: Section 1.4, also short notes on page 258 (about BCD) and page 76 (about Gray codes)
Fri Sep 13 A little bit more about sign/magnitude representations of integers. Introduction to two's-complement representations of integers. Two's-complement negation and addition.
Slides: Set 1, slides 44-57
Textbook reference: Section 1.4
Wed Sep 11 Conversion between binary, octal, and hexadecimal representations of integers. Signed and unsigned number systems. Unsigned binary addition. Introduction to binary sign/magnitude representation of integers.
Slides: Set 1, slides 22-44
Textbook reference: Section 1.4
Mon Sep 9 Representation of integers using bases ten, two, eight and sixteen. Conversion from one radix to another.
Slides: Set 1, slides 1-21
Textbook reference: Section 1.4
Fri Sep 6 Introduction to digital systems. Overview of course organization.
Slides: Fall 2019 Course Introduction
Textbook reference: Sections 1.1-1.3