# ENEL 353 - Digital Circuits

### Approximate Course Schedule

The University of Calgary
Department of Electrical and Computer Engineering

Norm Bartley and Steve Norman, Course Instructors
Fall Session, 2020

Below is an approximate lecture schedule for the course. We will attempt to cover all of the topics listed here. The amount of time given to each is our best (rounded) estimate, and is subject to change only slightly as the course progresses. The table refers to the sections of the required course textbook "Digital Design and Computer Architecture," by David M. Harris and Susan L. Harris, Second Edition, Morgan Kaufmann, 2013.

The textbook is available in the UofC Library in hard-copy form, or as an e-book.

 50-Minute Lectures Textbook sections Topics 3 1.4 Number systems and binary arithmetic; signed number repreentations 1 - Simple codes (from other textbooks): Binary Coded Decimal, Gray codes 3 1.5-1.6 Basic logic gates; logic voltage levels, noise margin 1 2.1 Introduction to combinational circuits 3 2.2-2.3 Boolean algebra: terminology, axioms, single- and multi-variable theorems, algebraic manipulation 1 2.4-2.5 Logic circuits, multi-level combinational circuits, hardware reduction 1 2.6 Illegal and floating logic values; tristate buffers 4 2.7 Karnaugh maps: overview, definitions (some from other textbooks), minimization of SOP and POS expressions, don't-cares, 5-variable maps 3 2.8 Combinational-circuit building blocks: multiplexers and decoders 2 2.9 Combinational-circuit timing: propagation and contamination delay; critical and short paths 3 3.1, 3.2.1-3.2.6 Introduction to sequential ciruits; latches and flip-flops, registers 1 3.3.1-3.3.2 Synchronous sequential circuits: properties and definitions 5 3.4 Finite State Machine (FSM) design; Mealy and Moore FSM models; FSM factoring, FSM analysis 3 3.5 Timing in sequential circuits; flip-flop timing, clock skew, metastability 3 5.5.1, 5.5.6 Introduction to memory arrays; Read-Only-Memories (ROMs), circuit design using ROMs 1 5.4 Sequential-circuit building blocks: synchronous counters and shift-registers