ENEL 353 - Digital Circuits

Laboratory Information, Synopsis, and Schedule

The University of Calgary
Department of Electrical and Computer Engineering

Norm Bartley and Steve Norman, Course Instructors
Fall Session, 2020

Four lab sessions are planned, as summarized below. Note that this schedule is tentative and is subject to change as the course progresses. If the schedule changes, you will be notified safely in advance.

An introduction to the lab and the four lab exercises will be posted to D2L as PDF documents. The exercises will be posted plenty of time in advance to give students time to prepare.

The labs are entirely online in Fall 2020. You may work alone or in pairs to complete each lab over a one-week period, starting on the scheduled date of your lab period:

All of the labs will use Intel Corporation's Quartus software and ModelSim simulator, both available for free from Intel's website. Detailed instructions on download and installation will be posted to D2L in the lab introductory document.

Laboratory 1: Introduction to Digital Circuits.

In this lab, you will learn how to describe basic logic functions with truth tables and to confirm experimentally the operation of such basic logic gates as AND, OR, XOR (exclusive OR), NOT, NAND, NOR, and XNOR. You will also construct and test simple binary adder circuits.
Section Date
B01 Monday, September 21, 2020
B02 Monday, September 28, 2020
B03 Tuesday, September 22, 2020
B04 Wednesday, September 30, 2020
B05 Wednesday, September 23, 2020
B06 Tuesday, September 29, 2020

Laboratory 2: Design and CPLD Implementation of Digital Arithmetic Circuits.

In this lab, you will design and implement circuits to perform digital arithmetic, including addition, subtraction, and integer multiplication.
Section Date
B01 Monday, October 5, 2020
B02 Monday, October 26, 2020
B03 Tuesday, October 6, 2020
B04 Wednesday, October 14, 2020
B05 Wednesday, October 7, 2020
B06 Tuesday, October 13, 2020

Laboratory 3: Design and Implementation of a Combinational Circuits.

In this lab, you will design combinational circuits at the gate level as well as to use such combinational circuit building-blocks such as decoders or multiplexers.
Section Date
B01 Monday, November 2, 2020
B02 Monday, November 16, 2020
B03 Tuesday, November 3, 2020
B04 Wednesday, November 18, 2020
B05 Wednesday, November 4, 2020
B06 Tuesday, November 17, 2020

Laboratory 4: Design and CPLD Implementation of Sequential Circuits.

In this lab, you will investigate flip-flop circuits, the main building blocks of sequential logic circuits. You will build and test various common types, including a level-triggered RS latch, a D latch, and. an edge-triggered D flip-flop (DFF). You will also design and test a synchronous sequential circuit.
Section Date
B01 Monday, November 23, 2020
B02 Monday, November 30, 2020
B03 Tuesday, November 24, 2020
B04 Wednesday, December 2, 2020
B05 Wednesday, November 25, 2020
B06 Tuesday, December 1, 2020

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